The present invention relates to providing two synchronous clock signals of unequal voltages and in particular to providing, on a BiCMOS chip, an ECL clock signal for driving a high-capacitance line and one or more higher-voltage synchronous CMOS clock signals for driving CMOS circuits.
BiCMOS integrated circuits are useful for providing, on a single chip, both the desirable switching speeds of bipolar devices and the desirably low surface area requirements of CMOS devices. Typically, a bipolar device of much small area can charge and discharge larger loads compared to a CMOS device. The bipolar devices on such a chip are typically clocked by a clock signal with a potential of about 1 volt, which is the typical voltage for emitter-coupled logic (ECL) type of bipolar devices. In many BiCMOS chips, the CMOS devices are not separately clocked. In cases which a separate clock signal is used for clocking the CMOS devices, such a separate clock signal is typically the result of translating the ECL clock signal to a second, higher voltage, such as about 5 volts.
In a typical BiCMOS device, at least one clock signal is applied to a high-capacitance clock signal distribution line or "C-wire". For purposes of the present discussion a high-capacitance line is a line with a capacitance greater than about 0.2 pf. Not uncommonly, clock signal distribution lines have a capacitance of 10 pf or more. In pure CMOS designs the 5 volt CMOS-level clock signal was used to drive the C-wire.